CIES Consortium

Industry – academic collaborationLSIs

R&D of technologies to automacally design environments for low-energy consumption and highly functional VLSI processors based on non-volatile devices

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    Prof.
    Takahiro Hanyu

To overcome a power-wall problem in 4x-nm CMOS era and beyond, our R&D project aims to develop nonvolatile (NV)-device-based logic-circuit Intellectual Properties (IPs) and its automatic design environment. In fact, we have been developing a CAD environment for NV field-programmable gate arrays (FPGAs). We have almost established the environment by combining an open-source CAD tool, called Verilog-to- Routing (VTR), with nonvolatile logic-circuit IPs. We have also been developing an NV-VLSI processor oriented place & route algorithm together with dedicated power-management control.

Fig.1

CAD flow for nonvolatile VLSI processor using VTR with nonvolatile circuit IPs

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